FFT implementation on DSP-chips-theory and practice

The problem of comparing different algorithms for the execution of the fast Fourier transform (FFT) is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an FFT implementation on different digital signal processors (DSPs) is used as a measure. It turns out that this more practical figure of merit yields a rather different valuation of the algorithms. Furthermore, a method to halve the table size for the radix-2 twiddle factors is described. Some new FFT programs for execution on DSPs are compared with programs provided by the manufacturers