Title :
50 nm Vertical Replacement-Gate (VRG) pMOSFETs
Author :
Sang-Hyun Oh ; Hergenrother, J.M. ; Nigam, T. ; Monroe, D. ; Klemens, F.P. ; Kornblit, A. ; Mansfield, W.M. ; Baker, M.R. ; Barr, D.L. ; Baumann, F.H. ; Bolan, K.J. ; Boone, T. ; Ciampa, N.A. ; Cirelli, R.A. ; Eaglesham, D.J. ; Ferry, E.J. ; Fiory, A.T. ;
Author_Institution :
Lucent Technol. Bell Labs., Murray Hill, NJ, USA
Abstract :
We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (<20 /spl Aring/) gate oxide.
Keywords :
MOSFET; ion implantation; 50 nm; channel doping; hyperthin gate oxide; ion implantation; p-channel vertical replacement gate MOSFET; source/drain extension; Doping; Etching; Fabrication; Ion implantation; MOSFETs; Rapid thermal processing; Reluctance generators; Surface contamination; Thermal engineering; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904260
