A fast method for MOS model evaluation in VLSI simulation with controllable error

Author

Cheng, C.W. ; Li, C.K.

Author_Institution

Dept. of Electron. Eng., Hong Kong Polytech., Hunghom, Hong Kong

fYear

1991

fDate

16-17 Jun 1991

Firstpage

200

Abstract

The authors present a tree-based model approximation (TBMA) MOSFET table model. With the method, the function domain of interest is partitioned recursively. Compared with an even partition strategy in a conventional table look-up, the partition size of a region inside the domain is large when the function is less nonlinear in that region and it is smaller if the function is more nonlinear. To reduce the dimension of the table, the gate-offset-voltage concept is used to shrink the three dimensional MOSFET model to a two dimensional model, maintaining the overall accuracy within a few percent. If smaller error is required, a TBMA correction table can be imposed to reduce the evaluation error to a specified value. Also, a new algorithm for constructing continuity partitions in the TBMA table is proposed

Keywords

MOS integrated circuits; VLSI; circuit analysis computing; digital simulation; errors; insulated gate field effect transistors; semiconductor device models; table lookup; 2D model; 3D model; MOS model evaluation; MOSFET table model; TBMA correction table; VLSI simulation; continuity partitions; controllable error; evaluation error; fast method; gate-offset-voltage concept; tree-based model approximation; two dimensional model; Circuit simulation; Computational efficiency; Computational modeling; Computer errors; Error correction; Linear approximation; MOSFET circuits; Partitioning algorithms; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on

Conference_Location

Shenzhen

Type

conf

DOI

10.1109/CICCAS.1991.184318

Filename

184318