4-16Mb DRAMs: Cost/performance tradeoffs

This panel will try to assess the relative merits of alternative circuit design techniques and technology choices for 4-16Mb DRAMs. To illustrate: by including additional masking steps, improved performance may be obtained at increased cost. Other topics to be discussed will include the critical charge for smaller cells, alternative cell designs, package constraints, internal voltage levels, and the best choice for interconnect. Finally, the expected time frames for experimental and production stages will be explored.