• DocumentCode
    2884669
  • Title

    A 4b × 4b multiplier and 3b counter in Josephson threshold logic

  • Author

    Hatano, Y. ; Harada, Y. ; Yamashita, Katsumi ; Kawabe, U.

  • Author_Institution
    Hitachi Central Research Laboratory, Tokyo, Japan
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    196
  • Lastpage
    197
  • Abstract
    This Paper will report on the development of a 4×4b parallel multiplier with a carry-to-carry delay time of 279ps and a 3b binary counter operating at 2.2 GHz implemented in Josephson junction technology.
  • Keywords
    Adders; Counting circuits; Current measurement; DC generators; Josephson junctions; Large scale integration; Magnetic circuits; Power amplifiers; Power generation; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156938
  • Filename
    1156938
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2884669