• DocumentCode
    2884740
  • Title

    A 50 µ A standby 1MW × 1b/256KW × 4b CMOS DRAM

  • Author

    Fujii, Shohei ; Saito, Sakuyoshi ; Okada, Yoshitaka ; Sato, Mitsuhisa ; Sawada, Syo ; Shinozaki, S. ; Natori, K. ; Ozawa, O.

  • Author_Institution
    Toshiba Semiconductor Development Engineering Laboratory, Kawasaki, Japan
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    266
  • Lastpage
    267
  • Abstract
    A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half Vcccc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well measuring 3.24μm2has resulted in a chip size of 4.4×12.3mm2with an access time of 56ns.
  • Keywords
    Boron; CMOS technology; Capacitance; Driver circuits; Flip-flops; Implants; Random access memory; Read-write memory; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156942
  • Filename
    1156942
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2884740