CMOS device scaling beyond 100 nm

CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.