Title :
Current and future low-k dielectrics for Cu interconnects
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Abstract :
Low-k/Cu integration with low-cost process is a key to future multilevel Cu damascene. This paper describes current status and future direction of low-k dielectrics for Cu interconnects. A novel direct patterning of low-k dielectric films by photochemical reaction is proposed as a future low cost multilevel interconnect technology. It is demonstrated that the smallest feature size of 50 nm damascene lines and via holes can be directly patterned in methylsilsesquiazane low-k dielectric films by electron beam lithography for the first time. In addition, a porous methylsilsesquiazane film is developed and evaluated as a candidate for future ultra-low-k dielectrics.
Keywords :
ULSI; copper; delays; dielectric thin films; electron beam lithography; integrated circuit interconnections; 50 nm; Cu; ULSI; dielectric films; direct patterning; electron beam lithography; feature size; low-k dielectrics; multilevel Cu damascene; multilevel interconnect technology; photochemical reaction; porous methylsilsesquiazane film; via holes; Costs; Delay; Dielectric films; Electromagnetic wave absorption; Electron beams; Lithography; Moisture; Photochemistry; Resists; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904304