Title :
An NMOS 64b floating-point chip set
Author :
McAllister, W. ; Zuras, D.
Author_Institution :
Hewlett-Packard Co., Cupertino, CA, USA
Abstract :
Three floating point arithmetic chips have been developed in a 1.5μm NMOS process. They are an adder, modified Wallace Tree multiplier, and a combinatorial divider. Speed of scalar operation is 490ns, 660ns and 1610ns, respectively.
Keywords :
Added delay; Adders; Approximation algorithms; Circuits; Floating-point arithmetic; Logic arrays; MOS devices; Pipelines; Propagation delay; Registers;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156964
