Title :
A 40K cache memory and memory management unit
Author :
Cho, Jeon-Wook ; Jin Kaku
Author_Institution :
Fairchild Semiconductor, Palo Alto, CA, USA
Abstract :
The development of a cache memory to support 32b microprocessors will be offered. Including an on-chip memory unit the circuit operates at 33MHz, delivers data to the CPU in 2/4 clock cycles and is fabricated in 2μm CMOS.
Keywords :
Buffer storage; CMOS technology; Cache memory; Clocks; Degradation; Engines; Memory management; Random access memory; Registers; System buses;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156968
