DocumentCode
2885319
Title
A 16ns CMOS EEPLA with reprogrammable architecture
Author
Rutledge, D. ; Turner, Jessica ; Darling, Robert ; Josephson, G.
Author_Institution
Lattice Semiconductor Corp., Hillsboro, OR, USA
Volume
XXIX
fYear
1986
fDate
19-21 Feb. 1986
Firstpage
240
Lastpage
241
Abstract
A PLA, whose architecture may be electrically programmed, will be described. The device has been built in 1.2μm EEPROM technology and operates at 20MHz with 380mW dissipation. On-chip scan diagnostics are used for testing.
Keywords
Capacitance; Circuit testing; Clocks; EPROM; Logic devices; Logic testing; Parallel programming; Programmable logic arrays; Registers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location
Anaheim, CA, USA
Type
conf
DOI
10.1109/ISSCC.1986.1156977
Filename
1156977
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