Title :
A bipolar 18K gate variable-size cell masterslice
Author :
Nishimura, T. ; Kato, Shigeo ; Tatsuki, M. ; Sato, Hikaru ; Kohara, M. ; Sakaue, K. ; Hirao, Takami ; Kuramitsu, Y.
Author_Institution :
Mitsubishi LSI Res. Dev. Laboratory, Itami, Japan
Abstract :
This paper will cover a 4-level metal, ECL array with variable size cells composed of units containing three transistors and four polysilicon resistors. A 32b multiplier implemented in this array uses 10.7K gate and operates in 17ns.
Keywords :
Degradation; Delay; Laboratories; Large scale integration; Logic functions; Logic gates; Macrocell networks; Resistors; Silicon; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156978
