• DocumentCode
    2885339
  • Title

    A bipolar 18K gate variable-size cell masterslice

  • Author

    Nishimura, T. ; Kato, Shigeo ; Tatsuki, M. ; Sato, Hikaru ; Kohara, M. ; Sakaue, K. ; Hirao, Takami ; Kuramitsu, Y.

  • Author_Institution
    Mitsubishi LSI Res. Dev. Laboratory, Itami, Japan
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    76
  • Lastpage
    77
  • Abstract
    This paper will cover a 4-level metal, ECL array with variable size cells composed of units containing three transistors and four polysilicon resistors. A 32b multiplier implemented in this array uses 10.7K gate and operates in 17ns.
  • Keywords
    Degradation; Delay; Laboratories; Large scale integration; Logic functions; Logic gates; Macrocell networks; Resistors; Silicon; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156978
  • Filename
    1156978
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2885339