Substrate enhanced degradation of CMOS devices

This paper investigates hot carrier induced nMOS and pMOS degradation in the presence of a substrate bias and compares the results with those of the conventional Channel Hot Carrier (CHC) regime. Stress experiments and detailed characterizations (including spatial profiling of the damage) were carried out on state of the art n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs. Results reveal that upon application of a substrate bias degradation becomes faster and more distributed towards the channel than in the channel hot carrier regime.