Title :
A 65 ns CMOS 1Mb DRAM
Author :
Webb, C. ; Creek, R. ; Holt, W. ; King, Grant W. ; Young, Ian A.
Author_Institution :
Intel Corporation, Hillsboro, OR, USA
Abstract :
This paper will cover a 5.3×9.6 mm CMOS 1Mb DRAM using a 28.5μm2/l transistor cell with a self-aligned contact. The memory array has been placed in an N-well reducing the soft error rate below 1000FITs without die coat.
Keywords :
CMOS technology; Capacitors; Delay; Differential amplifiers; Paper technology; Plastics; Random access memory; Read-write memory; Solid state circuits; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156984
