An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

Author

Radens, C.J. ; Kudelka, S. ; Nesbit, L. ; Malik, R. ; Dyer, T. ; Dubuc, C. ; Joseph, T. ; Seitz, M. ; Clevenger, L. ; Arnold, Norbert ; Mandelman, J. ; Divakaruni, R. ; Casarotto, D. ; Lea, D. ; Jaiprakash, V.C. ; Sim, J. ; Faltermeier, J. ; Low, K. ; Str

Author_Institution

Semicond. R&D Center, IBM Corp., Hopewell Junction, NY, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

349

Lastpage

352

Abstract

This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.

Keywords

DRAM chips; MOS memory circuits; cellular arrays; isolation technology; 16 Gbit; 4 Gbit; capacitor collar; device active area; isolation trench; line/space pattern; single bit contact; single-sided buried-strap node contact; trench-capacitor DRAM; trench-sidewall vertical device cell; Capacitors; Dielectric devices; Dielectric substrates; Dry etching; Fabrication; Optical imaging; Optical scattering; Polymers; Random access memory; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904327

Filename

904327