A layout system for double metal-layer gate array chips

Author

Xue, Hua ; Lee, Jinsong ; Qian, Liming ; Lee, Feng ; Chen, Song ; Tong, Jiarong ; Zhang, Kaihe ; Pushan Tang

Author_Institution

Dept. of Electron. Eng., Fudan Univ., Shanghai, China

fYear

1991

fDate

16-17 Jun 1991

Firstpage

423

Abstract

The authors present a layout system, FELLOW, for double metal-layer gate array chip designs. The system covers the complete layout design stages from netlist description to final physical layout. New ideas in design of system data management, technology design-rule independent, macro cell storage, base generation and human interface have been implemented in this system. The chip area comparison between 2 single metal layer chips and those of the FELLOW system showed up to 20% reduction by using the second metal layer. A so-called standard software environment, i.e. UNIX, C and X11 window, is adopted and the quantity of source code is about 95000

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; integrated logic circuits; logic CAD; logic arrays; CMOS ASIC; FELLOW; base generation; chip area; data management; double metal-layer gate array chips; human interface; layout system; macro cell storage; netlist description; physical layout; standard software environment; Chip scale packaging; Libraries; Redundancy; Routing; Software systems; Spatial databases;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on

Conference_Location

Shenzhen

Type

conf

DOI

10.1109/CICCAS.1991.184378

Filename

184378