DocumentCode
2885524
Title
Diagonal layout and surface strap trench (DST) cell [embedded DRAMs]
Author
Kajiyama, T. ; Aochi, H. ; Asao, Y. ; Morikado, M. ; Koyama, H. ; Sugimae, K. ; Ishibashi, S. ; Hosotani, K. ; Kito, M. ; Sato, A. ; Kido, M. ; Sakuma, M. ; Sato, M. ; Watanabe, S. ; Miyawaki, N. ; Hamamoto, T.
Author_Institution
Memory LSI Res. & Dev. Center, Toshiba Corp., Yokohama, Japan
fYear
2000
fDate
10-13 Dec. 2000
Firstpage
357
Lastpage
360
Abstract
The present paper proposes a new trench type cell, which has an advantage of realizing long retention time distribution, and also which is suitable for realizing first access speed characteristics because the DST cell has the larger cell capacitance, the smaller cell leakage current and the smaller parasitic resistance.
Keywords
DRAM chips; capacitance; cellular arrays; isolation technology; leakage currents; access speed characteristics; cell capacitance; cell leakage current; embedded DRAMs; parasitic resistance; retention time distribution; surface strap trench; trench type cell; Capacitance; Contact resistance; Etching; Fabrication; Leakage current; Monitoring; Random access memory; Surface resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-6438-4
Type
conf
DOI
10.1109/IEDM.2000.904329
Filename
904329
Link To Document