Title :
A novel bit-line process using poly-Si masked dual-damascene (PMDD) for 0.13 /spl mu/m DRAMs and beyond
Author :
Miyashita, Tadakazu ; Nitta, H. ; Nomura, Hideyuki ; Nakajima, Kensuke ; Sakata, A. ; Mizutani, Tomoko ; Minakata, Hideaki ; Tanaka, Mitsuru ; Tomita, Hiroki ; Kurahashi, Tetsuo ; Watanabe, Yoshihiro ; Kubota, Takahide ; Hatada, Akiyoshi ; Hosaka, Kazumot
Author_Institution :
Fujitsu Labs. Ltd., Yokohama, Japan
Abstract :
A novel middle-of-line (MOL) DRAM cell technology based on the poly-Si masked dual-damascene tungsten bit-line (BL) has been developed. New technologies such as borderless rectangular metal contacts, a thermally robust tri-layer barrier metal, well-controlled dry/wet recessed damascene BLs, and a low-temperature LPCVD-Si/sub 3/N/sub 4/ cap for a storage node self-aligned contact make it possible to realize the successful MOL integration for 0.13 /spl mu/m DRAMs. Since this process offers a sufficient alignment margin and a significant reduction of chip size as well as a reduced thermal budget, it is expected to be useful for making the future gigabit DRAMs and logic embedded DRAMs.
Keywords :
DRAM chips; MOS memory circuits; VLSI; cellular arrays; chemical vapour deposition; integrated circuit metallisation; masks; 0.13 micron; Si/sub 3/N/sub 4/; alignment margin; bit-line process; borderless rectangular metal contacts; chip size; dry/wet recessed damascene BLs; gigabit DRAMs; logic embedded DRAMs; low-temperature LPCVD; middle-of-line DRAM cell technology; polysilicon masked dual-damascene; storage node self-aligned contact; thermal budget; thermally robust tri-layer; Etching; Fabrication; Laboratories; Logic devices; MOS devices; Plugs; Random access memory; Robustness; Tin; Tungsten;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904330
