Title :
Two 64K CMOS SRAMs with 13ns access time
Author :
Flannagan, S. ; Reed, Patrick ; Voss, P. ; Nogle, S. ; Simon, Bernd ; Sheng, Dong-Sheng ; Kung, R. ; Barnes, John
Author_Institution :
Motorola MOS Memory Group, Austin, TX, USA
Abstract :
This report will cover the development of 64K×1 and 16K×4 CMOS SRAMS with access times of 13ns and power dissipation of 60mW at 10MHz. A 1.5μm double-metal, double-poly process was used. Array archtiecture allowing short lines, high-gain data path and asynchronous circuit techniques will be described.
Keywords :
Circuits; Delay; Fabrication; Power amplifiers; Read-write memory; Resistors; Stability; Testing; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156991
