Dense CMOS design of cellular neural networks with programmable synaptic weights

Author

Bang, Sa H. ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

3

fYear

1994

fDate

27 Jun-2 Jul 1994

Firstpage

1923

Abstract

Design of a continuous-time, shift-invariant CNN with digitally-programmable synaptic operators is described. In addition, the hardware annealing capacity is included to provide the maximum flexibility over a variety of applications such as image processing, unconstrained optimization, and generalized analog computing framework. The simulation results are also presented

Keywords

CMOS analogue integrated circuits; analogue multipliers; cellular neural nets; continuous time systems; neural chips; summing circuits; cellular neural networks; continuous-time, shift-invariant CNN; dense CMOS design; generalized analog computing framework; hardware annealing capacity; image processing; maximum flexibility; programmable synaptic weights; unconstrained optimization; Analog computers; CMOS technology; Cellular neural networks; Computational modeling; Computer networks; Concurrent computing; Hardware; Image processing; Neural engineering; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-1901-X

Type

conf

DOI

10.1109/ICNN.1994.374454

Filename

374454