Title :
Improving neural hardware performance with network structural design guidelines
Author :
Naylor, David ; Jones, Simon
Author_Institution :
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
fDate :
27 Jun-2 Jul 1994
Abstract :
To realise the cost-performance benefits of specialist neural architectures, application designers must be able to effectively exploit the available hardware resources to maximise performance. This paper investigates how the structure and size of each layer in a network, mapped into a linear systolic array of neural processors, influences the performance and utilisation efficiency of the hardware. The analysis of multilayer perceptron networks reveals that those which exhibit certain structural characteristics have higher bandwidth, lower latency and make more efficient use of their hardware resources. A set of design guidelines are presented which summarise the salient structural features of these networks
Keywords :
backpropagation; integrated circuit design; multilayer perceptrons; neural chips; neural net architecture; systolic arrays; HANNIBAL; cost-performance benefits; higher bandwidth; linear systolic array; lower latency; multilayer perceptron networks; network structural design guidelines; neural hardware performance; Artificial neural networks; Bandwidth; Computer architecture; Guidelines; Multi-layer neural network; Multilayer perceptrons; Neural network hardware; Neural networks; Neurons; Systolic arrays;
Conference_Titel :
Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-1901-X
DOI :
10.1109/ICNN.1994.374463
