Improving neural hardware performance with network structural design guidelines

To realise the cost-performance benefits of specialist neural architectures, application designers must be able to effectively exploit the available hardware resources to maximise performance. This paper investigates how the structure and size of each layer in a network, mapped into a linear systolic array of neural processors, influences the performance and utilisation efficiency of the hardware. The analysis of multilayer perceptron networks reveals that those which exhibit certain structural characteristics have higher bandwidth, lower latency and make more efficient use of their hardware resources. A set of design guidelines are presented which summarise the salient structural features of these networks