Power Bus Transients in Very High Speed Logic Systems

Developments in fine line photolithography and improved control over processing parameters are the basis for newly emerging families of high performance integrated circuits. The number of transistors per chip and the data processing speed will be increased in the foreseeable future by at least an order of magnitude over the present state of the art. In addition to silicon IC technology, gallium arsenide and related compounds show considerable promise, with demonstrated gate delays as low as 12 psec. It has been recognized that the improved performance of these ICs can be exploited only if significant advances are made in packaging technology. The chip decoupling capacitor, traditionally mounted on the circuit board as a discrete element, must become an integral part of the package or chip carrier in order to minimize its associated inductance. It is not as well appreciated, however, that the entire power delivery system, including the power supply and intermediate decoupling elements, may also limit the performance of high speed ICs. Resonances in the power distribution and decoupling network at frequencies well below that of the system clock are shown to be potentially major sources of ripple. Proper design of the system to avoid these resonances requires a unified approach that considers all elements from the power supply to the chip decoupling capacitor. To facilitate such a design, power converters mounted on the circuit board close to their loads are recommended.