Title :
Implementation of a fully parallel Kohonen map: a mixed analog digital approach
Author :
Peiris, Vincent ; Hochet, Batrand ; Declercq, Michel
Author_Institution :
Swiss Federal Inst. of Technol., Lausanne, Switzerland
fDate :
27 Jun-2 Jul 1994
Abstract :
This paper describes the CMOS implementation of a digitally behaving Kohonen map. Although input values and synaptic weights are quantized, the basic blocks are implemented using digital or analog techniques where best suited, combined with efficient information encoding. This has lead the authors to the design of a modular 4×4 Kohonen neuron chip that may be cascaded in order to realize large size fully parallel Kohonen maps
Keywords :
CMOS integrated circuits; VLSI; analogue processing circuits; learning (artificial intelligence); neural chips; parallel architectures; self-organising feature maps; CMOS implementation; digitally behaving Kohonen map; fully parallel Kohonen map; input values; mixed analog digital approach; modular 4×4 Kohonen neuron chip; synaptic weights; CMOS technology; Circuits; Convergence; Encoding; Equations; Hardware; Neural networks; Neurons; Vectors; Very large scale integration;
Conference_Titel :
Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-1901-X
DOI :
10.1109/ICNN.1994.374531
