Title :
A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores
Author :
Takao, Y. ; Kudo, H. ; Mitani, J. ; Kotani, Y. ; Yamaguchi, S. ; Yoshie, K. ; Kawano, M. ; Nagano, T. ; Yamamura, I. ; Uematsu, M. ; Nagashima, N. ; Kadomura, S.
Author_Institution :
Manuf. Technol. Dev., Fujitsu Labs. Ltd., Mie, Japan
Abstract :
This paper describes a 0.11 /spl mu/m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 /spl mu/m gate transistor, and 2.2 /spl mu/m/sup 2/ 6T-SRAM cell are realized by using KrF 248 nm lithography, optical proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63 mA//spl mu/m and 0.28 mA//spl mu/m are realized for nMOSFET and pMOSFET with 0.11 /spl mu/m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 /spl mu/m CMOS technology with copper/FSG interconnects.
Keywords :
CMOS digital integrated circuits; MOSFET; SRAM chips; copper; integrated circuit interconnections; logic gates; low-power electronics; proximity effect (lithography); ultraviolet lithography; 0.11 micron; 248 nm; CMOS technology; Cu; KrF lithography; NAND gate; SRAM cell; copper interconnect; drain current; gate shrinkage; interlayer dielectric; low-power design; nMOSFET; optical proximity effect correction; pMOSFET; propagation delay; system-on-a-chip; very-low-k interconnect; CMOS technology; Copper; Dielectrics; High speed optical techniques; Leakage current; Lithography; Optical design; Optical interconnections; System-on-a-chip; Wiring;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904381
