A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

Author

Tyagi, S. ; Alavi, M. ; Bigwood, R. ; Bramblett, T. ; Brandenburg, J. ; Chen, W. ; Crew, B. ; Hussein, M. ; Jacob, P. ; Kenyon, C. ; Lo, C. ; Mcintyre, B. ; Ma, Z. ; Moon, P. ; Nguyen, P. ; Rumaner, L. ; Schweinfurth, R. ; Sivakumar, S. ; Stettler, M. ; T

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

567

Lastpage

570

Abstract

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; copper; integrated circuit interconnections; low-power electronics; 1.3 V; 130 nm; 18 Mbit; 70 nm; CMOS SRAM; Cu; Cu dual damascene interconnect; NMOS transistor; PMOS transistor; drive current; dual threshold voltage transistor; gate oxide; logic technology; Boron; CMOS technology; Integrated circuit interconnections; Isolation technology; Logic; MOS devices; MOSFETs; Random access memory; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904383

Filename

904383