VLSI implementation of binary relation inference network in solving shortest path problems

Analog VLSI design in implementing a binary relation inference network to solve shortest path problems is presented. With this connectionist approach, it is able to solve shortest path problems in a time that is practically independent of the problem size. This is possible due to the parallel and asynchronous operating nature of the network, which allows the computational units to process the signals in the continuous-time domain. An OTA based adder, a magnitude preserving minimum finding circuit and a tri-state comparator are the key building blocks in building the inference network. Simulation results and worst case analysis of the building blocks are also described