Title :
A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications
Author :
Ootsuka, F. ; Wakahara, S. ; Ichinose, K. ; Honzawa, A. ; Wada, S. ; Sato, H. ; Ando, T. ; Ohta, H. ; Watanabe, K. ; Onai, T.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 130 nm node CMOS technology with a self-aligned contact system is demonstrated. Tensile stress of the contact etch stop increases nFET´s Ids, and reduces compressive stress caused by shallow trench isolation, which enhances pFET´s Ids. A 1.92 /spl mu/m/sup 2/ 6T-SRAM has been integrated with high performance transistors.
Keywords :
CMOS memory circuits; SRAM chips; etching; integrated circuit technology; internal stresses; isolation technology; 130 nm; CMOS technology; SRAM cell; compressive stress; drain current; etch stop; nMOSFET; pMOSFET; self-aligned contact; shallow trench isolation; system-on-a-chip; tensile stress; CMOS technology; Compressive stress; Etching; Intrusion detection; Large-scale systems; Niobium compounds; Plasma applications; Plasma materials processing; Silicon compounds; Tensile stress;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904385
