A high-drive CMOS buffer for high capacitive loads

Author

Nosratinia, Aria ; Ahmadi, M. ; Jullien, G.A. ; Shridhar, M.

Author_Institution

Dept. of Electr. Eng., Windsor Univ., Ont., Canada

fYear

1991

fDate

16-17 Jun 1991

Firstpage

648

Abstract

A CMOS buffer for high capacitive loads is presented. The objective of the design has been a high-power, area-efficient buffer to be used in very large scale analog applications. The use of compensation capacitor has been avoided and therefore a significant saving of die area has been achieved. This was made possible by using two half-circuits at the input and eliminating the intermediate stage, and also resistive compensation at the output stage. The buffer can deliver a slew rate of 1.2 V/μs to capacitive loads in excess of 5000 pF. It has a total harmonic distortion of less than 3% at 20 kHz. At stand-by, it consumes only 125 μA (0.625 mW). The buffer occupies 100 mils² of die area in a 3 μm technology

Keywords

CMOS integrated circuits; VLSI; buffer circuits; driver circuits; linear integrated circuits; operational amplifiers; 0.625 mW; 125 muA; 20 kHz; 3 micron; 5 V; 5000 pF; area-efficient buffer; capacitive loads; half-circuits; high-drive CMOS buffer; resistive compensation; saving of die area; slew rate; total harmonic distortion; very large scale analog applications; CMOS technology; Design methodology; Filtering; Frequency response; Large-scale systems; Pins; Switched capacitor circuits; Switching circuits; Total harmonic distortion; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on

Conference_Location

Shenzhen

Type

conf

DOI

10.1109/CICCAS.1991.184440

Filename

184440