A low power and high-speed current latched comparator for weak current operations

Author

Weng, Ro-Min ; Chiang, Chia-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

245

Abstract

A low power and high-speed current latched comparator for weak current operations is proposed in This work. The current latched comparator consists of a preamplifier stage and a track-and-latch stage. The differential preamplifier is designed to minimize the clock feedthrough errors using two transresistance circuits. For the track-and-latch stage, a very high-speed unit is adopted to increase the speed of the comparator. With tsmc 0.18μm CMOS technology, the current comparator achieves the simulation results of 20nA resolution at sampling rate up to 150MHz with a 1.5 V supply voltage.

Keywords

CMOS analogue integrated circuits; current comparators; current-mode circuits; differential amplifiers; low-power electronics; preamplifiers; 0.18 micron; 1.5 V; 150 MHz; 20 nA; CMOS technology; clock feedthrough error; differential preamplifier; low power high-speed current latched comparator; preamplifier stage; track-and-latch stage; transresistance circuit; weak current operation; CMOS technology; Circuit simulation; Clocks; Delay; Parasitic capacitance; Preamplifiers; Rails; Sampling methods; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412738

Filename

1412738