Electrical Failure Analysis Methodology for DRAM of 80nm era and beyond using Nanoprober Technique

In this paper, the electrical failure analysis for DRAM of design rule as 80 nm and beyond by using nanoprober technique was described. We have successfully measured and evaluated electrical characteristics of periphery and cell array transistors of 80 nm DRAM using nanoprober. Measurements for Metal Contact (MC), Bit Line (BL) and Bit Line Contact (BLC) probing were proceeded and compared with Test Element Group (TEG) probing results. Interconnect Characterization Environment (ICE) simulation was also carried out to verify the current decrease of BLC probing results. Measurement for characteristics of memory cell array transistors, which had 150 nm pitch, of 80 mn DRAM was possible. It is concluded that a direct probing method using the nanoprober technique was an useful tool of the electrical failure analysis for 80 nm DRAM and beyond generations.