Analysis of spatial and temporal behavior of threedimensional multi-core architectures towards run-time thermal management

3D integration provides number of advantages such as improved interconnectivity and packaging density, which can provide higher performance microprocessors as well as better memory hierarchies. Yet thermal characteristics limit the potential performance improvement in many cases. In this study we investigate the thermal behavior of high performance and high power microprocessor stacks, focusing on 3D-specific challenges. We investigate both the static/spatial and temporal behavior of microprocessor stacks towards assessing feasibility of stacking alternatives and effective management of on-chip temperatures.