A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology

Author

Fujii, M. ; Nii, K. ; Makino, H. ; Ohbayashi, S. ; Igarashi, M. ; Kawamura, T. ; Yokota, M. ; Tsuda, N. ; Yoshizawa, T. ; Tsutsui, T. ; Takeshita, N. ; Murata, N. ; Tanaka, T. ; Fujiwara, T. ; Asahina, K. ; Okada, M. ; Tomita, K. ; Takeuchi, M. ; Shinohar

Author_Institution

Renesas Technol. Corp., Itami

fYear

2007

fDate

19-22 March 2007

Firstpage

131

Lastpage

134

Abstract

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

Keywords

CMOS logic circuits; CMOS memory circuits; fault diagnosis; flip-flops; integrated circuit design; integrated circuit testing; integrated circuit yield; large scale integration; random-access storage; CMOS process; TEG; fail bit maps; failure location detection; flip-flop RAM; large-scale integration; logic LSI; logic circuit fault diagnosis; process technology; size 65 nm; yield optimization; CMOS logic circuits; CMOS process; CMOS technology; Flip-flops; Large scale integration; Large-scale systems; Logic design; Mass production; Random access memory; Testing; Large-scale integration; Logic circuit fault diagnosis; SRAM; Yield optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on

Conference_Location

Tokyo

Print_ISBN

1-4244-0781-8

Electronic_ISBN

1-4244-0781-8

Type

conf

DOI

10.1109/ICMTS.2007.374469

Filename

4252419