Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution

As the performance of a processing system is to be significantly enhanced, on-chip many-core architecture plays an indispensable role. Explorations of a suitable three-dimensional integrated circuit (3D IC) with through-silicon via (TSV) to realize a large number of processing units and highly dense interconnects certainly attract the attention. However, the combination of processors, memories, and/or sensors in a die stack leads to the cooling problem in a tottering situation. Consequently, a thermal solution which has a high heat removing rate seems unavoidable. The floorplan and routing of the chip should be rearranged after the thermal solution is performed. By utilizing the thermal ridge, the routing spaces between hot core-groups (CGs) need to be expanded until they cannot affect each other. Under the constraint of 20% area overhead for the thermal ridges, we place the thermal ridges with different densities of thermal TSVs between the hottest CGs on the chip. For a 1024-core network on chip (NoC) design studied in this paper, the maximum temperature decreases from 408 K to 372 K, and the temperature nonuniformity is improved from 3.8 K/cm to 0.5~1.5 K/cm. This means that the temperature difference between two neighboring CGs is less than 0.06 K. Compared with micro-fluidic cooling channel, the proposed thermal ridge scheme is much more cost-effective and easy to implement.