RLC signal integrity analysis of high-speed global interconnects [CMOS]

Author

Xuejue Huang ; Yu Cao ; Sylvester, D. ; Shen Lin ; King, T.-J. ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

731

Lastpage

734

Abstract

Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.

Keywords

CMOS integrated circuits; delays; high-speed integrated circuits; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; wiring; RLC signal integrity analysis; capacitive coupling effects; current-return paths; delay; high-speed buses; high-speed global interconnects; inductive coupling effects; noise; shield wires; worst-case switching patterns; CMOS technology; Capacitance; Copper; Crosstalk; Delay; Frequency; Inductance; Inverters; Signal analysis; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904422

Filename

904422