Title :
A 256-element associative parallel processor
Author :
Jalowiechi, I. ; Lea, R.
Author_Institution :
Brunel University, Uxbridge, England
Abstract :
A 145K transistor, 2μm CMOS parallel processor capable of executing 262-million 8b additions/s will be detailed. Under the control of an external sequencer, the chip has been used to perform a 3×3 8b convolution in 95μs for image processing applications.
Keywords :
Array signal processing; Associative processing; CMOS process; CMOS technology; Clocks; Driver circuits; Image processing; Logic arrays; Parallel processing; Process design;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157086
