DocumentCode
2887224
Title
A VLSI chip set for a massively parallel architecture
Author
Grondalski, R.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
198
Lastpage
199
Abstract
This paper will described two chips fabricated in 2μms CMOS. One chip contains 32 processors, and performs 320 million 4bit operations/s. The other chip a communications router, is capable of a throughput of 160Mbytes/s.
Keywords
Circuit testing; Delay; Fabrication; Parallel architectures; Protocols; Registers; Switching circuits; Throughput; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157087
Filename
1157087
Link To Document