Title :
A sub-micron CMOS echo canceller using a DSP cell
Author :
Takahashi, Hiroki ; Fujii, Shohei ; Kawauchi, Kiyoto ; Inaba, Takaaki ; Gambe, Hirohisa
Author_Institution :
Fujitsu Ltd., Semiconductor Devices Laboratory, Atsugi, Japan
Abstract :
This report will cover a 45K gate chip designed using a silicon compiler. A 11.5×11.8mm die contains a DSP that was available as a pre-designed cell.
Keywords :
CMOS technology; Digital signal processing; Echo cancellers; Logic gates; Low voltage; Propagation delay; Read only memory; Routing; Signal processing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157089
