DocumentCode
2887257
Title
A sub-micron CMOS echo canceller using a DSP cell
Author
Takahashi, Hiroki ; Fujii, Shohei ; Kawauchi, Kiyoto ; Inaba, Takaaki ; Gambe, Hirohisa
Author_Institution
Fujitsu Ltd., Semiconductor Devices Laboratory, Atsugi, Japan
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
148
Lastpage
149
Abstract
This report will cover a 45K gate chip designed using a silicon compiler. A 11.5×11.8mm die contains a DSP that was available as a pre-designed cell.
Keywords
CMOS technology; Digital signal processing; Echo cancellers; Logic gates; Low voltage; Propagation delay; Read only memory; Routing; Signal processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157089
Filename
1157089
Link To Document