Causes and dynamics of LDPC error floors on AWGN channels

It is well-known that the performance of low-density parity-check codes is compromised by the emergence of an error floor, which is caused by so-called trapping sets. By identifying the dominant trapping sets, this error floor can be estimated analytically using a linear model. In this paper, this linear approach is improved to make the analysis more accurate. Then, guided by the error probability formula, a simple but effective method to improve the code performance in the error floor region is proposed, by introducing a boosting factor to the log-likelihood ratios returned from unsatisfied check nodes during the early decoding stages. It is shown that the effect of the dominant trapping sets can thus be reduced. The dominance of trapping sets can be further reduced by extending the computational range of the LLRs at the decoder. To illustrate these ideas, a short regular LDPC code constructed by Tanner, as well as the IEEE 802.3 LDPC code, are studied.