Title :
A 6K gate array with self-test and maintenance
Author :
Anderson, F. ; Brzozwy, R. ; Metzgar, S.
Author_Institution :
Motorola IC Applications Research Laboratory, Phoenix, AZ, USA
Abstract :
A gate array fabricated in a 1.25μm double metal technology will be discussed. A built in self-test and maintenance circuit occupies 8% of the 308×314mil die. An on-chip supply voltage translation circuit is also included.
Keywords :
Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Logic testing; Registers; Sequential analysis; System testing; Transfer functions;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157090
