A microprogrammable parallel architecture for DSP

The implementation of a parallel architecture for DSP is mandatory for the high performance execution of many real time digital signal processing algorithms. On the other hand, coarse grain parallel architectures are useful only for the algorithms that do not need an intensive data exchange among processors and suffer poor flexibility. The parallel architecture described in the paper allows most of the DSP algorithms to be efficiently mapped onto a mono- or bi-dimensional processor array. Moreover the system architecture can be specialized by changing directly the control flow of each node in the array: after the configuration phase each node works independently without any further instruction fetching (the algorithm is not translated in a sequence of standard operations, but it is directly mapped in the control unit of each node). The keypoint of the system is the capability of microprogramming each node of the architecture so that the specific algorithm can be split into elementary part, optimally mapped onto a generic computation node