DocumentCode
2887311
Title
An ECL gate array hardened against soft errors
Author
Okabe, Masayuki ; Tatsuki, M. ; Sakaue, K. ; Hirao, Takami ; Kuramitsu, Y.
Author_Institution
Mitsubishi LSI Research and Development Laboratory, Hyogo, Japan
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
152
Lastpage
153
Abstract
A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.
Keywords
Clocks; Computer errors; Error analysis; Integrated circuit reliability; Laboratories; Large scale integration; Logic circuits; Logic design; Logic devices; Research and development;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157091
Filename
1157091
Link To Document