DocumentCode
2887345
Title
A 60ns CMOS DSP with on-chip instruction cache
Author
Caren, C. ; Benjamin, Bruce ; Boddie, J. ; Fuccio, M. ; Gadenz, R. ; Hays, W. ; McMillan, L. ; Henry, Joseph ; Bays, L. ; Gupta, Arpan ; Klinikowski, J. ; Goh Komoriya ; Rigge, L. ; Willenbecher, D. ; Kaichuen Wong
Author_Institution
AT&T Bell Laboratories, Holmdel, NJ, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
156
Lastpage
157
Abstract
A 16b fixed point programmable DSP with a 60ns instruction cycle time will be discussed. Fabricated in twin tub, 1μm CMOS, the chip includes 2K words of ROM, 512 words of RAM and an instruction cache for fast vector operations.
Keywords
CMOS technology; Cache memory; Clocks; Digital signal processing; Digital signal processing chips; Random access memory; Read only memory; Read-write memory; Registers; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157092
Filename
1157092
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