BSIM4 gate leakage model including source-drain partition

Author

Cao, K.M. ; Lee, W.-C. ; Liu, W. ; Jin, X. ; Su, P. ; Fung, S.K.H. ; An, J.X. ; Yu, B. ; Hu, C.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

815

Lastpage

818

Abstract

Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

Keywords

MOSFET; leakage currents; semiconductor device models; tunnelling; BSIM4; advanced CMOS processes; compact MOSFET modeling; dielectric leakage current; direct-tunneling mechanisms; gate leakage model; intrinsic gate leakage model; physical source/drain current partition; CMOS process; Dielectrics; Equations; Gate leakage; Leakage current; MOS capacitors; MOS devices; MOSFET circuits; Semiconductor device modeling; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904442

Filename

904442