Title :
Measurement of die stress distributions in flip chip CBGA packaging
Author :
Roberts, Jordan ; Hussain, Safina ; Rahim, M. Kaysar ; Motalab, Mohammad ; Suhling, Jeffrey C. ; Jaeger, Richard C. ; Lall, Pradeep ; Zhang, Ron
Author_Institution :
Dept. of Mech. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder re flow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10- - minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.
Keywords :
assembling; ball grid arrays; ceramic packaging; flip-chip devices; integrated circuit interconnections; microprocessor chips; piezoresistive devices; reflow soldering; sensors; solders; stress measurement; thermal management (packaging); CTE ceramic chip carrier; adhesive cure; assembly process; ceramic LGA package; data acquisition hardware; die stress distribution measurement; flip chip CBGA packaging; lead free solder interconnects; lid attachment; microprocessor die; on-chip piezoresistive stress sensor; packaging architecture; sensor resistance measurement; silicon die; silicon sensor rosettes; solder cure; solder reflow; solder underfill dispense; stress change; test chip wafer; thermal cycling; three-dimensional stress state; Assembly; Ceramics; Flip chip; Packaging; Semiconductor device measurement; Sensor phenomena and characterization; Silicon; Stress measurement; Testing; Thermal stresses;
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2010 12th IEEE Intersociety Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-5342-9
Electronic_ISBN :
1087-9870
DOI :
10.1109/ITHERM.2010.5501285