Title :
A new analytical delay and noise model for on-chip RLC interconnect
Author :
Yu Cao ; Xuejue Huang ; Sylvester, D. ; Chang, N. ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
In this paper, we develop a 2/sup nd/ order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1/sup st/ order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input parameters.
Keywords :
crosstalk; delays; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; timing; analytical delay model; coupled RLC lines; current return paths; decoupling; delay results; distributed RLC waveform model; input parameters; noise model; on-chip RLC interconnect; overshoot effects; second-order model; Analytical models; Capacitance; Coupled mode analysis; Crosstalk; Damping; Delay effects; Inductance; Propagation delay; SPICE; Signal analysis;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904444
