Title :
Throughput enhancement strategy of maskless electron beam direct writing for logic device
Author :
Inanami, R. ; Magoshi, S. ; Kousai, S. ; Hmada, M. ; Takayanagi, T. ; Sugihara, K. ; Okumura, K. ; Kuroda, T.
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Japan
Abstract :
A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P and R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.
Keywords :
cellular arrays; electron beam lithography; logic devices; logic device; logic synthesis; maskless electron beam direct writing; pattern design; place and route; semiconductor circuit; standard cell; throughput; Apertures; Circuit synthesis; Design methodology; Electron beams; Fabrication; Libraries; Lithography; Logic devices; Throughput; Writing;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904446
