Implementation of an LMS adaptive filter on an FPGA employing multiplexed multiplier architecture

In this paper, a multiplexed multiplier architecture (MMA) for a field programmable gate array (FPGA) implementation of the least mean square (LMS) adaptive filter is developed and presented. In the proposed architecture, hardware multipliers are reused, i.e. multiplexed in time, for both filtering and adaptation. The number of multipliers may be chosen to achieve certain design trade-offs. The design trade-offs considered in this paper include on-chip area, filter size, maximum filter throughput, and power consumption.