A novel algorithm for ordering gate sequence for gate matrix layout

Gate matrix is a layout style for MOS (NMOS or CMOS) integrated circuits. A novel algorithm to determine the optimal gate sequence in gate matrix layout is presented. The algorithm depends on a predictor-and-adaptor procedure which is implemented on IBM-PC/AT and SUN workstations in C language. The algorithm reduces CPU time (10-20)% and reduces the number of rows (5-15)% compared with Asano´s algorithm respectively. The authors give a more efficient heuristic approach to deal with the gate sequencing problem of NP-completeness and analyze the probability property of the algorithm