Design analysis of a distributed arithmetic adaptive FIR filter on an FPGA

Distributed arithmetic (DA) is an efficient architecture for implementing finite impulse response (FIR) digital filters. The DA FIR filter calculates the filter output using look up tables (LUTs) instead of multipliers. Thus, a DA based implementation of an FIR filter is highly parameterizable and area efficient. Furthermore, the fundamental building blocks in the DA architecture map well to the architecture of today´s field programmable gate arrays (FPGAs). In this paper, we analyze the design of an adaptive FIR filter using the DA architecture on an FPGA. The design trade-offs discussed in detail include throughput, number of logic elements utilized, memory usage, and power consumption estimates.