DocumentCode :
2887648
Title :
A novel implantless MOS thin-film transistor with simple processing, excellent performance and ambipolar operation capability
Author :
Lin, H.C. ; Lin, C.Y. ; Yeh, K.L. ; Huang, R.G. ; Wang, M.F. ; Yu, C.M. ; Huang, T.Y. ; Sze, S.M.
Author_Institution :
Nat. Nano Device Labs., Hsin-Chu, Taiwan
fYear :
2000
fDate :
10-13 Dec. 2000
Firstpage :
857
Lastpage :
859
Abstract :
A novel thin-film transistor (TFT) device that requires no implant step and is capable of ambipolar operation is proposed and successfully demonstrated. The new structure features an undoped Si active channel, a tap metal field-plate (i.e., the sub-gate), and Schottky source/drain. The equivalent circuit of the device is given. During device operation, a high fixed voltage is applied to the sub-gate to form a field-induced source/drain layer under the sub-gate region. Depending on the polarity of the sub-gate bias, the device can be set for n-channel operation with positive sub-gate bias, and p-channel operation with negative sub-gate bias. The new device is similar to conventional Schottky barrier (SB) MOSFET devices, with the exception of a field-induced source/drain region between the channel and Schottky source/drain. The existence of the field-induced source/drain region serves to supply abundant channel carriers during on-state, while reducing the notorious off-state leakage that has plagued all previous SB MOSFETs. The new device is also similar to MOSFETs with field-induced drain (FID), except that the heavily-doped source/drain region is replaced by Schottky source/drain. While retaining all the advantages of FID such as low off-state leakage and low junction leakage, the use of Schottky source/drain not only reduces processing steps (i.e., implant and annealing), but also allows ambipolar operation, thus greatly simplify processing steps especially for CMOS process integration.
Keywords :
Schottky barriers; annealing; equivalent circuits; heavily doped semiconductors; leakage currents; thin film transistors; CMOS process integration; Schottky source/drain; ambipolar operation capability; annealing; channel carriers; equivalent circuit; field-induced source/drain layer; field-induced source/drain region; fixed voltage; heavily-doped source/drain region; implantless MOS thin-film transistor; junction leakage; n-channel operation; off-state leakage; p-channel operation; polarity; positive sub-gate bias; sub-gate region; tap metal field-plate; Annealing; CMOS process; Doping; Equivalent circuits; Fabrication; Implants; Laboratories; Schottky barriers; Thin film transistors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
Type :
conf
DOI :
10.1109/IEDM.2000.904452
Filename :
904452
Link To Document :
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